Alesis QS7.1 Manuel de service télécharger pdf (Page 19)

Alesis QS Series Keyboards Service Manual V1.00 11/19/06

It helps to know the initial state of the active devices in the circuit. While the raw supply

is just below the raw supply threshold Q5 Q5 Q5 is turned off, allowing the base of Q6 Q6 Q6

to be pulled high via R40 R38 R62 , turning it on. This in turn holds the voltage across C15

C42 C59 at 0.7V (approximately ground). These in turn keeps the input to the first inverter

U7A U9C U19A low. Thus RST is high and RST is low. In addition, the S6 incorporates an

extra inverter (U7E) to drive the power up mute circuit (see Section 2.24).

The process begins when the raw +5V supply reaches the reset threshold. The voltage

divider consisting of R52, R39 and D6 R36, R37 and D9 R60, R61 and D10 scales the level of

the raw supply so that Q5 Q5 Q5 turns on at the preset threshold. This pulls the base of Q6

Q6 Q6 to 0.7V (low) turning it off. This allows the voltage across C15 C42 C59 to charge

slowly via R41 R39 R63 (this also adds a time delay that prevents raw supply ripple from

triggering multiple resets). Once this voltage rises above the threshold level of the Schmidt

Trigger inverter it switches states, pulling RST low and RST high, completing the reset cycle.

2.31B The GAL and Memory Mapped I/O

While the H8 has been optimized as a controller device, it is none the less somewhat

limited in the number of direct input and output lines available. Memory mapping is the simplest

method of allowing software designers the ability to manipulate the large number of hardware

registers directly from the microprocessor with a minimum of external hardware.

The idea is to “fool” the microprocessor into thinking that hardware register locations

(latches) are actually memory locations. The process begins when the H8 sets up the address

buss. The GAL (U12 U13 U9) checks this address to see if it is in the range of hardware

registers. If the H8 address is within the confines of normal memory, the RAM or ROM signal is

asserted and memory is accessed normally. However if the address is in the hardware range,

the GAL decodes the address and strobes the chip select line of the appropriate device. Each

device must interpret the state of the microprocessor ReaD and WRite lines and send or

receive data appropriately. It is left up to the software to “know” which devices are written to as

opposed to read from.

2.31C Other Processor I/O

All other “outside world” communication of the processor not handled via memory

mapped I/O (See Previous Section) is sent and received via the H8’s built in I/O ports. These

are automatically configured by the software at power up. These lines all have internal pullup

resistors. These “outside world” devices include pedals, front panel key switches. and pitch,

mod, and data wheel inputs.

2.31D MIDI

MIDI input is opto isolated (U4 U7 U14) from the MIDI Input Jack (J7 J12 J8). R2 R35

R49 current limits the incoming signal while D3 D7 D6 serves to protect the opto isolator from

reverse bias currents. R42 R40 R51 serves to set the internal threshold level of the opto

isolator while R22 R41 R50 augments the internal pullup of the H8’s input port.

MIDI output is initiated from the H8’s output port. Two elements of a Schmidt Trigger

inverter (U7C and U7D U9B and U9E U19E and U19B) are used to buffer the outgoing signal.

This signal is current limited (R1 R45 R53) before being sent to the MIDI Output Jack (J8 J13

J9).

In addition, the QS7, QS8, and QSR incorporate a similarly designed MIDI THRU (U9A

and U9F U19C and U19D, R45 R55, J14 J10).

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 96 97

Commentaires sur ces manuels

Pas de commentaire

Alesis QS7.1 Manuel de service Page 19

Commentaires sur ces manuels

Produits connexes et manuels pour Pianos numériques Alesis QS7.1